A variety of systems and techniques are known for stacking packaged integrated circuits. Some techniques are devised for stacking chip-scale packaged devices (CSPs) while other systems and methods are better directed to leaded packages which exhibit a set of leads extending from at least one lateral side of a typically rectangular package.
Memory devices are packaged in both chip-scale (CSP) and leaded packages. However, techniques for stacking CSP devices are typically not optimum for stacking leaded devices. Although CSP devices are gaining market share, in many areas integrated circuits continue to be packaged in high volumes in leaded packages. For example, the well-known flash memory integrated circuit is typically packaged in leaded packages with fine-pitched leads emergent from one or both sides of a package. A common package for flash memory is a fine pitch thin small outline package commonly known as the TSOP. Flash circuitry in TSOP packaging typically differs from common TSOP-packaged DRAMs in that flash TSOPs typically exhibit fine pitch leads emergent from the shorter pair of the lateral sides of the package while DRAM TSOPs typically exhibit leads emergent from the longer pair of sides of the package.
The assignee of the present invention, Staktek Group L.P., has developed a wide variety of techniques, systems and designs for stacks and stacking with both leaded and CSP devices. In leaded package stacking, Staktek Group L.P. has developed rail bus systems that interconnect the leads of stacked leaded IC devices by use of rails. The present assignee also owns, for example, U.S. Pat. No. 6,572,387 issued Jun. 3, 2003 and U.S. patent application Ser. No. 10/449,242 published as Pub. No. 2003/0203663 A1 which disclose and claim various techniques and apparatus related to stacking leaded packages.
Many other techniques have been developed that use various means for interconnecting the leads of the stacked devices. For example, U.S. Pat. No. 4,696,525 to Coller et al. teaches a socket connector for coupling adjacent devices in a stacked configuration to one another. The socket has external conductors that interconnect leads from like, adjacent devices to one another. Sockets, however, are limited in several respects. They are not versatile in their ability to implement complex interconnections. In addition, such sockets, which have relatively thick, plastic bodies, act as heat insulators between adjoining upper and lower (major) package surfaces, which can inhibit the module's overall ability to dissipate heat.
Although the art has many techniques for stacking leaded devices, a new system and method for stacking leaded package devices is a welcome development. Accordingly, the present application discloses improved systems and methods for electrically and thermally coupling adjacent integrated circuit devices in stacked modules.